The present invention generally relates to a Bi-CMOS logic circuit, and more particularly to an improvement in the rise and fall characteristics of an output signal from the Bi-CMOS logic circuit.
As is well known, a Bi-CMOS logic circuit is composed of a bipolar element and a CMOS (complementary metal oxide semiconductor transistor) element. Referring to FIG. 1, there is illustrated a conventional Bi-CMOS logic circuit, which includes a CMOS inverter composed of a P-channel MOS transistor MP1 and an N-channel MOS transistor MN1 and a pair of bipolar transistors Q1 and Q2. The Bi-CMOS logic circuit has a high operating speed characteristic afforded by the bipolar transistor pair and a low power consumption characteristic afforded by the CMOS inverter. A resistor R1 (impedance circuit) is connected between the base and emitter of the bipolar transistor Q1 and a resistor R2 (impedance circuit) is connected between the base and emitter of the bipolar transistor Q2. An output terminal OUT of the Bi-CMOS logic circuit is grounded through a wiring load capacitance C, which is a parasitic capacitance.
The bipolar transistors Q1 and Q2 are connected in series between a positive power source Vcc and a negative power source (ground). The output signal from the Bi-CMOS logic circuit is drawn from a connection node at which the emitter of the bipolar transistor Q1 is connected to the collector of the bipolar transistor Q2. The MOS transistor MP1 is connected between the collector and base of the bipolar transistor Q1. The MOS transistor MN1 is connected between the collector and base of the bipolar transistor Q2. An input signal applied to an input terminal IN is supplied to the gates of the MOS transistors MP1 and MN1.
When the input signal (also indicated by IN) changes from a high (H) level (approximately equal to the power source voltage Vcc) to a low level (approximately equal to the ground potential), the MOS transistor MP1 is switched from OFF to ON. In response to this change in the state of the MOS transistor MP1, the bipolar transistor Q1 is turned ON. Thus, the wiring load capacitance C is charged so that the output signal (also indicated by OUT) at the output terminal OUT is changed from the low level to the high level.
During the time when the voltage of the output terminal OUT increases to a potential equal to Vcc-V.sub.BE (base-emitter voltage of the bipolar transistor Q1), most of current passes through the bipolar transistor Q1. This is due to the fact that the current drivability of the bipolar transistor Q1 is greater than that of the MOS transistor MP1. The current passing through the bipolar transistor Q1 charges the wiring load capacitance C. When the collector-emitter voltage of the bipolar transistor Q1 becomes equal to or greater than the base-emitter voltage V.sub.BE thereof, the bipolar transistor Q1 cannot pass current. In this state, the wiring load capacitance C is charged by a current passing through the MOS transistor MP1 and the resistor R1. Thereby, the voltage of the output terminal OUT gradually increases toward the power source voltage Vcc and finally becomes equal to the high level (approximately equal to Vcc).
On the other hand, when the input signal changes from the low level to the high level, the MOS transistor MP1 is switched from ON to OFF and the MOS transistor MN1 is switched from OFF to ON. In response to this change in the state of the MOS transistor MN1, the bipolar transistor Q2 is turned ON. Thus, the wiring load capacitance C is discharged through the bipolar transistor Q2 so that the voltage of the output terminal OUT is changed from the high level to the low level. Until the time when the voltage of the output terminal OUT decreases to the base-emitter voltage V.sub.BE of the bipolar transistor Q2, most of current passes through the bipolar transistor Q2. This is due to the fact that the current drivability of the bipolar transistor Q2 is greater than that of the MOS transistor MN1. When the collector-emitter voltage of the bipolar transistor Q2 becomes equal to or less than the base-emitter voltage V.sub.BE thereof, the bipolar transistor cannot pass current. Thus, the wiring load capacitance C is gradually discharged through the MOS transistor MN1 and the resistor R2 and finally becomes equal to the low level (approximately equal to the ground potential).
A description will now be given of the disadvantages of the above-mentioned conventional Bi-CMOS logic circuit with reference to FIG. 2. FIG. 2 is a waveform diagram of the output signal OUT obtained at the output terminal OUT. A letter "a" denotes the potential difference between the emitter and base of the bipolar transistor Q1, and a letter "b" denotes the potential difference between the emitter and base of the bipolar transistor Q2. A letter "c" denotes the time it takes the output voltage to increase by the potential difference "a", and a letter "d" denotes the time it takes the output voltage decreases by the potential difference "b".
As shown in FIG. 2, the signal waveform of the output signal OUT rises rapidly. After that, during the time "c", the current passing through the resistor R1 charges the wiring load capacitance C so that the voltage of the output terminal OUT increases gradually by the base-emitter voltage V.sub.BE of the bipolar transistor Q1. The time when the current is passing through the wiring load capacitance C is based on the time constant of R1 and C. Thus, it takes a long time for the output voltage to increase to the high level so that a rounding of the waveform of the output signal appears during the time "c". Similarly, during the time "d", the current from the wiring load capacitance C passes through the resistor R2 so that the wiring load capacitance is gradually discharged. Thus, a rounding of the falling waveform of the output signal appears during the time "d". Thus, the period at which the output signal is maintained at the high level (approximately equal to Vcc) is short, which causes jitter, particularly when the Bi-CMOS logic circuit operates at high frequencies.